I am a little bit confusing between pipelined datapath as well as pipelined control processor, what is the distinction between these two? Also, I've found out some websites that state the term 'pipelined / unpipelined system' and I would also like to have some explanation about this. With regard to the question mentioned above, the answer is '>1, short' but I am not able to figure out the logic behind the answer so please help me with that too.
Usually, there are three terms: single cycle, multi cycle, and pipelined; also there is datapath and control.
The single cycle processor will execute each instruction in one longer cycle, thus its CPI is 1, and its cycle time is the time it takes for the critical path in the larger hardware circuitry, usually the datapath for the load type instructions.
The multi cycle processor will execute each instruction in several (e.g. 4-5) shorter cycles, so CPI of 4-5 cycles per instruction. The cycle time will be shorter, and assuming constant cycle time, then the cycle time will reflect the max of the critical paths of all hardware in each cycle.
The pipelined processor will execute each instruction in 5 shorter cycles, with the 5 cycles of one instruction overlapping with the cycles of other instructions so that the processor can be executing up to 5 instructions at the same time. Given that, the maximum CPI is 1, since 1 instruction completes every cycle, though various hazards slow it down from that max in most workloads. Cycle time is also the max of the critical paths of the 5 cycles.
Datapath refers to information that is typically word sized, so 32 bits wide on a 32-bit processor. The two 32-bit inputs & one 32-bit output from the ALU are datapaths, for example. Some datapaths are shorter than 32-bits, for example, register numbers are 5 bits wide and immediates are 16 bits wide.
Control paths refer to signals, usually 1 bit wide, that control which circuits are looked at vs. ignored. The control signals are set up differently for each different kind of instruction. The hardware is a merge of all the different circuitry needed for all possible instructions. Only some of the hardware is used for each individual instruction, but all has to be there in order to execute all the different instruction kinds. Most control signals go to control of some MUX, which chooses one of two datapaths to forward (and hence ignores the other). Some control signals are multi-bit, as in the ALU control, since the ALU operation needs several bits to differentiate between add, or, and, sub, compare, etc..
It doesn't make sense to me to have pipelined datapath but unpipelined control in the same processor implementation. If the processor is pipelined, that would apply to both datapath and control.
Both the single cycle and the multi cycle processor are unpipelined, as pipelining refers to that overlap of cycles from the execution of one instruction with those of another. This overlap causes hazards that are not present in the unpipelined processors, as a next instruction starts before the prior finishes.