I am attempting to design a simple CPU and I ma using SystemVerilog to design and ModelSim to simulate the design. I am trying to set up some code to count the number of instances of a specific module. I am currently using static variables to try to achieve this however it is not working. My code is as follows.
module testbench;
logic a0, b0, y0;
logic a1, b1, y1;
logic a2, b2, y2;
AND and0(.a(a0), .b(b0), .y(y0));
AND and1(.a(a1), .b(b1), .y(y1));
AND or0(.a(a2), .b(b2), .y(y2));
initial
begin
$display("AND Gates : ", and0.instance_count);
$display("OR Gates : ", or0.instance_count);
end
endmodule
module AND(input logic a, b, output logic y);
static int instance_count = 0;
initial
instance_count++;
and(y, a, b);
endmodule
module OR(input logic a, b, output logic y);
static int instance_count = 0;
initial
instance_count++;
or(y, a, b);
endmodule
The output this gives is 1 instance for both the AND gates and OR gates, which is incorrect. How could I change my code to fix this issue? In addition to this, a solution to this problem which can be determined through modelsim and not require me to add any code to my model would be an ideal solution, if that is possible.
All declarations at the module level are already static, and each module instance has a separate allocation of variable instances.
You could create a global package with an associative array.
package inst;
int count[string] = '{default:0};
endpackage
module AND(input logic a, b, output logic y);
initial inst::count["AND"]++;
and(y, a, b);
endmodule
SystemVerilog has no built-in introspection, but there are ways of building it in to your flow if you really want to dive into the VPI details.
But many tools including ModelSim have Tcl commands like
find instances -r /testbench/* -file instances.txt
that would be easy to write a counting script of individual instances.