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concurrencyprocesssignalsvhdl

Difference between process and concurrent statements


when I assign Signal F the complement of Signal B in a process like this:

architecture V1 of E is 
 signal B: bit; 
begin 
 process (A) begin 
  B<=A; 
  F<=not b; 
 end process; 
end architecture; 

then F will hold the old negated value of B in the first cycle.

But why doesn't the same hold for this example where I'm just using concurrent statements?

architecture V1 of E is 
 signal B : bit; 
begin 
  B<=A; 
  F<=not b; 
end architecture; 

When I'm thinking of the Hardware components F will receive the signal from B so in the first cycle F should also hold the old negated value of B?


Solution

  • Concurrent signal assignments are just shorthand for processes. Your second code is the same as:

    process(A)
    begin
      B <= A;
    end process;
    
    process(b)
    begin
      F <= not b;
    end process;
    

    The reason why the behavior differs is that with your first code the process resumes only when signal A changes while with the second each process resumes each time the signal in its sensitivity list changes.