I m working on an nRF52840 µc ,the µc will be woken up every 3 hours and i have to save a data(4bytes) into a tab[16] so i can send those 16 values later after 2 days.
Not familiar with the part but looking at the reference manual, the on-chip RAM is static meaning that it will retain its value so long as the power supply is maintained - even in sleep modes or through a reset. You would need to set-up the link map and start-up code to avoid initialising the reserved area on start-up.
Alternatively, the 256K flash memory is divided into 4K erase-block pages, you could reserve an entire page (i.e. set the link map to avoid locating code there). The flash endurance is only 10000 erase cycles, but even if you erases the block every two days, it would last >54 years. Since you are writing a data block of only 64 bytes you could write the blocks sequentially through the 4K such that the highest addressed non-blank block of 64 bytes is the current data; then you need only erase the page once it is entirely full, extending the endurance to 3500 years.
Note however that the flash as some restrictions:
That is to say you can write say 0xFFFFFF00, then 0xFFFF00FF, and the word would then contain 0xFFFF0000, but you could not then write the upper two bytes of that word.
Another issue with using the Code Flash is that while erasing, the bus stalls and instructions cannot be fetched. That means your code stops running. This scan be a serious issue in real-time systems; but given that your system sleeps for 3 hours at a time, presumably there are no critical micro-second level timing deadlines?
Another possibility offered by part is the UICR (User information configuration registers), a special area of non-volatile memory that includes 32 words (128 bytes) of customer defined data. However that is perhaps not very practical for dynamic storage since the area contains Nordic reserved words and device configuration, and like regular flash memory an erase deleted the entire UICR, so you would necessarily copy the data before erase and rewrite it. Not really power fail safe. The endurance is still 10000 erase cycles, if you striped it like above, having only 128 bytes would extend the endurance to 20000 cycles or 109 years erasing every 4 days.
Beyond those possibilities an off-chip NV memory device such as an EEPROM, FRAM, Flash, or even and SD/MMC card (with a filesystem). These can be attached via one of the available SPI, I2C (TWI) or QSPI interfaces. Whist likely to have higher endurance than the on-chip flah, that may still be a consideration for some devices. FRAM has no endurance issues, and SD cards are so capacious that it is unlikely to be an issue in the application described.