To introduce some randomness in my testbench I would like to use pseudo-random numbers seeded with the current Unix time or epoch. Is there a (non-synthesizable ofc) function in VHDL for that? I need it to work in VHDL 2008.
Why not simply passing a generic parameter value on the same command line you use to run the simulation? Example with bash
:
entity foo is
generic(seed: natural := 0);
end entity foo;
architecture bar of foo is
begin
assert false report natural'image(seed);
end architecture bar;
$ ghdl -a --std=08 foo.vhd
$ ghdl -r --std=08 foo
foo.vhd:7:3:@0ms:(assertion error): 0
$ ghdl -r --std=08 foo -gseed=$(date +%s)
foo.vhd:7:3:@0ms:(assertion error): 1648027085