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vhdlvivado

VHDL: using only portion of outport


I have an entity instantiated that has an out port of 32 bits. I only need bits 4 through 15 which will go into some signal s_a. I thought I could instantiate it this way but Vivado does not like it:

WHATEVER: entity work.example_entity
  port map(
    o_port( 15 downto 4 ) => s_a
  );

I know you can do something analogous with in ports and Vivado seems ok with that so long as I set all the bits to something like so:

WHATEVER2: entity work.other_entity
  port map(
    i_port( 7 downto 4 ) => ( others => '0' ),
    i_port( 3 downto 0 ) => s_b
  );

where i_port is an in port and s_b is some appropriately sized and typed signal.

Is there some way to only extract a subset of bits from an out port without connecting the entire port to a full-width signal and extracting the bits from that?


Solution

  • Like user16145658 said, the answer is "no." The open keyword only works on a whole out port, all bits included, and cannot be used on individual bits. If you use any of the bits in an out port then they all have to go somewhere.