I would like to write a driver and software that:
the software asks for data every twenty seconds ,and the hardware writes data to the DMA buffer and raises an interrupt when it’s done.
Unfortunately I have no experience writing drivers,and I can't use the Xilinx IP core which already has Driver.
The PCIe IP Core I use is UltraScale+ Device Integrated Block for PCI Express (PCIe).
I have implemented a simple driver that can read the status register on FPGA. And I follow these steps to implement DMA:
//Driver_Probe
pci_set_master(pdev);
drv_priv->virt_addr = kmalloc(2048, GFP_DMA);
if (!drv_priv->virt_addr)
{
dev_err(dev, "Failed to kmalloc");
err = -ENOMEM;
return err;
}
drv_priv->bus_addr = pci_map_single(pdev, drv_priv->virt_addr, 2048, PCI_DMA_FROMDEVICE);
if (!drv_priv->bus_addr)
{
dev_err(dev, "Failed to allocate DMA buffer");
err = -ENOMEM;
return err;
}
What else do I need to add to achieve this driver?
It is said that the data in the buffer cannot be read until the action is unmapped in the documentation. How can I successfully read the data after unmapping?
Are there any complete examples? The references I found were too brief for newbies.
I will be grateful for any help.
I wrote a tutorial to transfert data from FPGA to CPU RAM with PCIe some years ago but it's with a CycloneV.
In short:
/* Allocate and initialize shared control data */
dmas->dmabuff = dmam_alloc_coherent(&pdev->dev, BUFF_SIZE, &dmas->dma_handle, GFP_KERNEL);
if (!dmas->dmabuff){
printk("Error, can't alloc coherent\n");
goto err_return;
}
writel((unsigned long)(dmas->dma_handle), &dmas->bar0[CRA_REG_A2P_ADDR_MAP_LO0/4]);
In this example, the dma address configuration register is located under BAR0 in CRA_REG_A2P_ADDR_MAP_LO0
.
Once, PCIe core in FPGA have the buffer address, it will be able to read/write to CPU RAM.
It's an old tutorial, maybe Linux API changed a little bit now. But the spirit remain the same I think.