ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks

Question

I am new to VHDL and writing program for receiving the serial data, which is dependent on 2 clocks and one RESET signal. One is FPGA's main source clock and another one is the external SPI master clock.

The written is like below:

    process(reset, main_clk, ext_clk)               
    begin
        if(reset = '0') then
        rx_data <= x"0000";
            elsif(chip_sel = '0') then
                if(ext_clk'event and ext_clk = '1') then    
--              rx_data <= rx_data;
                    if(main_clk'event and main_clk = '1') then
                    --- receiving data serially

But Xilinx tool is giving error:

ERROR:Xst:1534 - Sequential logic for node <rx_data> appears to be controlled by multiple clocks.

How to overcome this error?

Answer 1

It's because you use 'event on ext_clk and main_clk which the tools use to infer clocks. Your design should only be sensitive to main_clk and reset. De