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veriloglookup-tablesregister-transfer-level

FPGA LUTs for combinational logic

I'm having trouble finding direct answers to how FPGA-level LUTs are accessed/implemented in simple modules (I'll provide an example below). Referring to the top answer on this post, https://electronics.stackexchange.com/questions/163961/creating-a-verilog-code-for-4-bit-multiplier-using-lookup-table, the type of LUT I'm trying to understand is the first one listed (FPGA-level).

For example, let's say I had the following module:

module RightRotation
{
  input logic clk
  input logic [2:0] din
  output logic [2:0] dout
};

always@(clk) begin
  dout[0] <= din[2];
  dout[1] <= din[0];
  dout[2] <= din[1];
end
endmodule

If I were to implement this module with a FPGA-level LUT with 3 inputs and 1 output, how many lookups would it take (for instance, is a value looked up every time a value is assigned with a nonblocking statement in the always@)? How would this answer change if I had 4, or 5, or 6 inputs?

Solution

  • After fixing syntax errors, Vivado produces these results for utilization and implementation.

    N inputs would use N flops in your design.

    enter image description here

    Vendor datasheets can help understand look up tables, CLBs, slices etc.
    Example here:
    https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf