Entity port declaration without direction: Why is it allowed and what did I create here?

Question

I just had to check something in an older module and found the following entity declaration:

entity myOldModule is
  port 
  (
    clk:   in std_logic;
    reset: in std_logic;
    data:  in std_logic;
    valid: std_logic;
    ...
  );
end myOldModule;

Note the missing in in the valid port declaration. It's also missing in the component declaration in the higher level module. It does however compile and behave as expected. So my questions are:

a) Why is this allowed by the VHDL syntax? I thought port list syntax was: port_name: mode data_type;

b) What is the equivalent structure created by this statement? Does the port just default to in? I'm guessing, non-toplevel entity ports just flatten out to regular signals but nothing ever works in VHDL if not done the correct way. So what happened here?

Using LatticeDiamond 12.3 or ModelSim 2020.3 and compiling using VHDL2002 and neither ever complained (at least not with an error).

Answer 1

As one source (VHDL 2000) of the standard says in chapter 4.3.2, or another source (VHDL 2008) in chapter 6.5.2:

If no mode is explicitly given in an interface declaration other than an interface file declaration, mode in is assumed.