After some searching, I cannot seem to find the answer to my question on creating subtypes of enumerated types in VHDL.
If I have a type describing the states of my state machine e.g.
type state_machine is (idle, reset, state1, state2, state3); -- all the way to a further 'n' number of states
I may have two signals using the state type i.e.
signal state_signal0 : state_machine := idle;
signal state_signal1 : state_machine := state1;
However, take the case that the state_signal1 signal only ever uses a subset of the state types e.g. let us say that it is only ever assigned state1 or state2. Is it possible to generate a subtype of the state_machine type.
In my head it would look something like this:
type state_machine is (idle, reset, state1, state2, state3);
subtype state_machine_subset is state_machine(state1, state2);
signal state_signal0 : state_machine := idle;
signal state_signal1 : state_machine_subset := state1;
So far I haven't found a way to achieve something like this because all of the subtype examples are described as finding ranges within integers and assigning them positive or natural etc. Would someone be able to shine a light on this?
A) Is this type of subtype definition possible?
B) If it is possible, is it worth doing? i.e. does it provide any synthesis benefits?
Thanks
In the specific case, where state1 to state2 spans a range of values, it is possible to define the subtype as:
subtype state_machine_subset is state_machine range state1 to state2;
Though, this is not generally applicable, since it is not possible to also generate a subtype with for example only idle and state3, since these does not span a range.
In synthesis this may save some bits, if the tool identifies the restricted value range. Tools does identify limited value range, for example when an integer subtype is defined like subtype int_0_7 is integer range 0 to 7;, which will usually yield a 3 bit value.
In simulation the subtype will generate an error if assigned outside the range, which is useful to improve test quality.