Unwanted Asynchronous Reset

Question

I have written the following VHDL code with the assumption that it will generate a counter with a synchronous reset! however, when I looked at the elaborated design in Vivado 2020.2, the counter has an ASYNCHRONOUS reset! The process should not get evaluated without seeing the rising/falling edges of the clock! How did the tool infer an asynchronous reset?!

PS. count is defined as an unsigned signal (not std_logic_vector)

Any explanation is greatly appreciated!

process(clk)
    begin
        if rst='1' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
end process;

Answer 1

Synthesis tools generally ignore the sensitivity list, and create the logic from design patterns in the code. In your code, the rst branch overrides the clock branch, hence it creates an asynchronous reset. In addition, the reset is not reliant on clk.

To create a synchronous reset, the rst branch should be inside the clock branch as the reset should only occur on a clock edge.

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;

    if rst = '1' then 
      count <= (others => '0');
    end if;
  end if;
end process;