Search code examples
packagevhdl

Declaration of an enumeration type in a package


I prefer to declare an enumeration type in a package so that I can use it in multiple entities. Here is my simplified code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use work.polar_package;

entity Decoder is
    port (
        clk : in std_logic;
        reset : in std_logic
    );
end entity Decoder;

architecture behavioral of Decoder is
    signal state : polar_package.state_type;
begin
    top_modul : process (clk)
    begin
        if clk = '1' and clk'event then
            if reset = '1' then
                state <= p0;
            else

            end if;
        end if;
    end process top_modul;
end architecture behavioral;

And I have declared and defined "state_type" in package "polar_package" as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package polar_package is
    type state_type is (p0 , p1 , p2);
end package polar_package;

package body polar_package is

end package body polar_package;

However, I see the below compilation error: Unknown identifier "p0"

is there any workaround for this?


Solution

  • please try:

    state <= polar_package.p0;