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Concatenation VHDL (2 8-bit vectors)

I was just wondering, how could I concatenate two 8 bit vectors together into a 16-bit vector with odata_H having the MSB and odata_L having the LSB? Any help would be appreciated. The vectors are data points given off from an ADT7420 temperature sensor.

signal BCD:             std_logic_vector(11 downto 0);
signal Bin_Temp:        std_logic_vector(7 downto 0);
signal Bin_Acc:         std_logic_vector(7 downto 0);
signal Buff_Temp:     std_logic_vector(7 downto 0);
signal Buff_Acc:      std_logic_vector(7 downto 0);
signal odata_L:         std_logic_vector(7 downto 0);
signal odata_H:         std_logic_vector(7 downto 0);
signal notEN:           std_logic;
signal odataT:          std_logic_vector(15 downto 0);
   begin
odataT <= odata_H & odata_L;
Bin_Temp <= odataT(8 downto 1);
notEN <= not(EN);
Solution

  • I don't know why in this case the concatenation apparently doesn't work. Nevertheless, another way of achieving it is by using the resize() function of the numeric_std library.

    library ieee;
use ieee.numeric_std.all;

[...]
odataT <= std_logic_vector(resize(signed(odata_H), odata_L'length));

    The concatenation (odata_H, odata_L) will be resized with a length of length (16 in this case). Of course unsigned instead of signed is possible, if applicable.