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c++gem5

gem5: Use xbar stat in BaseCPU


I have created a new stat of type Formula in the xbar.cc/hh files. There I aggregate all the different transDist types. I'd like to use this newly created stat to compute another stat in the BaseCPU object. What is the best way to have access to it (i.e., allTransactions stat) from BaseCPU? Is there any way to make it globally accessible?


Solution

  • I ended up having a direct line of comminication between the xbar and the CPU objects.

    I implemented a function in the Xbar object that returns the statistic that I want, called getAllTrans(). From the CPU object, I call that function and get the value of the statistic. The communication is implemented using the code below.

    // Research (Memory Boundedness)
    void
    BaseCPU::getAllTrans() {
        allTrans = 0;
    
        Cache *dCache = dynamic_cast<Cache*>
                (this->getPort("dcache_port", 0).getPeer().getOwner());
        if (dCache) {
            Cache *l2Cache = dynamic_cast<Cache*>
                    (dCache->getPort("mem_side", 0).getPeer().getOwner()->
                    getPort("mem_side_ports", 0).getPeer().getOwner());
            if (l2Cache) {
                CoherentXBar *membus = dynamic_cast<CoherentXBar*>
                (l2Cache->getPort("mem_side", 0).getPeer().getOwner());
                if (membus) {
                    allTrans = membus->getAllTrans();
                }
            }
            else {
                CoherentXBar *membus = dynamic_cast<CoherentXBar*>
                (l2Cache->getPort("mem_side", 0).getPeer().getOwner());
                if (membus) {
                    allTrans = membus->getAllTrans();
                }
            }
        }
    }
    

    The code above assumes that the dcache exists.

    Cache *dCache = dynamic_cast<Cache*>
                (this->getPort("dcache_port", 0).getPeer().getOwner());
    

    The code above points to the dcache object from the cpu. The hops are like this:

    CPU -> CPU port to dCache -> Peer of that port (i.e., dCache port to the CPU) -> Owner of that port (i.e., the dCache itself).

    I build on top of every object connecting the CPU to the Xbar until I reach the XBar. This isn't the most elegant solution but I haven't found a better one for getting information from one gem5 object to another one.