VHDL - Error comparing std_logic_vector with declared constant unsigned? The unsigned has been cast to std_logic_vector

Question

I am trying to create a Seven Segment Display controller in Vivado 2020.2 using VHDL 2008. The entity needs to be parametrizable by system clock rate and time to display each digit in the display (there are 8 digits). Here is the code I have so far:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;

entity SevenSeg is
    generic (
        -- Rate in HZ
        CLK_RT          : integer := 100000000;
        -- Time in ms
        DISPLAY_TIME    : integer := 20
    );
    port (
        clk             : in std_logic;
        rst             : in std_logic;
        dataIn          : in std_logic_vector(31 downto 0);
        digitDisplay    : in std_logic_vector(7 downto 0);
        digitPoint      : in std_logic_vector(7 downto 0);
        anode           : out std_logic_vector(7 downto 0);
        segment         : out std_logic_vector(7 downto 0)
    );
end SevenSeg;

architecture rtl of SevenSeg is
    constant ROLL_OVER : unsigned := to_unsigned(20 * 1000000 / (1000000000 / CLK_RT), 32);
    signal cnt       : std_logic_vector(31 downto 0);
    signal anode_sel : std_logic_vector(2 downto 0);
begin

     process (clk)
     begin
         if (clk'EVENT AND clk = '1') then      
             if rst = '1' then 
                 anode_sel <= (others => '0');
             else if cnt = std_logic_vector(ROLL_OVER) then
                 anode_sel <= anode_sel + 1;
             end if;
         end if;
     end process;
end rtl;

With the current state of the code, Vivado is flagging a syntax error "near end process." I am pretty sure something is wrong with cnt = std_logic_vector(ROLL_OVER) because when I comment that part of the if clause out, there is no longer any syntax errors. I have been researching comparisons in vhdl as well as the constant unsigned/vector types and nothing seems to be working. I would appreciate any insight into what is causing this error.

Answer 1

There are two alternatives, either with elsif:

if rst = '1' then 
   anode_sel <= (others => '0');
elsif cnt = std_logic_vector(ROLL_OVER) then
   anode_sel <= anode_sel + 1;
end if;

or: else if

if rst = '1' then 
   anode_sel <= (others => '0');
else
   if cnt = std_logic_vector(ROLL_OVER) then
      anode_sel <= anode_sel + 1;
   end if;
end if;