When writing test benches, is there any problem with writing
wait for 1 ns ; wait until rising_edge( clock ) ;
every time I want to wait for the next rising edge?
I'd like to put this sequence in a procedure and then always use it.
The reason I want to wait for 1 ns is that if I simply have the wait untils and there is no signal assignment in between two of them, they will collapse into one.
The clock cycle time is 10ns, so 1 ns shouldn't be a problem. What I'd really like to do is wait for one delta, but I don't know how to do that. Is it possible?
Are there hidden pitfalls to this approach?
We're using VHDL 93 with the ISIM simulator.
You don't need the wait for 1 ns.
One way to wait for 5 clocks is:
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
One simplified rule is that the wait statement always suspends the process for at least a simulation/delta cycle.
With a wait until that does not have an explicitly supplied on sensitivity-list (such as the example above), there is an implied on sensitivity-list that has every signal in the until clause in it. Hence, the above is equivalent to:
wait on clock until rising_edge( clock ) ;
wait on clock until rising_edge( clock ) ;
wait on clock until rising_edge( clock ) ;
wait on clock until rising_edge( clock ) ;
wait on clock until rising_edge( clock ) ;
Maybe this longer form is a little more obvious - when clock changes and rising_edge( clock ) is true the wait statement will resume and continue to the next wait statement. The next wait statement suspends until a change on clock occurs.