SystemVerilog property pass by reference

Question

Is it possible to pass a signal to a property by reference? For example, I want to create a cover property to capture a register changing, and re-use this property for dozens of different registers. I'd like to do something like this:

property reg_change(int num_cycles, ref bit some_reg);
    @(posedge CLK)
    $changed(some_reg) |-> ##num_cycles $changed(some_reg);
endproperty

Reg1Change10Cycles_cp : cover property (reg_change(10, reg1);
Reg2Change10Cycles_cp : cover property (reg_change(10, reg2);
//...

But I get a compile error for trying to use 'ref' in the property. I don't think I can just use bit some_reg since that would be pass-by-value, and won't ever see some_reg change. Is there anyway I can achieve this behavior without defining the entire property in each cover property?

Answer 1

There is no way and no need to pass formal arguments by reference to properties and sequences. Formal arguments to assertion constructs are replaced inline by the actual arguments. So in a sense they are always by reference. See section 16.8 Declaring sequences in the IEEE 1800-2017 SystemVerilog LRM. The same argument behavior applies to properties.

BTW, you should leave assertion arguments typeless unless you need strong typing rules to keep your assertion expression evaluating correctly.