VHDL function that alters record fields disrupts untouched fields in Vivado Simulation

Question

I've spent too much time on this and am completely confused. I have a record type:

--t_dp_sosi record
TYPE t_fft_sosi_out IS RECORD  -- Source Out or Sink In
sync     : STD_LOGIC;   
bsn      : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);      -- ctrl
re       : STD_LOGIC_VECTOR(c_fft_out_dat_w-1 DOWNTO 0);            -- data
im       : STD_LOGIC_VECTOR(c_fft_out_dat_w-1 DOWNTO 0);            -- data
valid    : STD_LOGIC;                                           -- ctrl
sop      : STD_LOGIC;                                           -- ctrl
eop      : STD_LOGIC;                                           -- ctrl
empty    : STD_LOGIC_VECTOR(c_dp_stream_empty_w-1 DOWNTO 0);    -- info at eop
channel  : STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0);  -- info at sop
err      : STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0);    -- info at eop (name field 'err' to avoid the 'error' keyword)
END RECORD;

and make an array type of it as such: TYPE t_fft_sosi_arr_out IS ARRAY (INTEGER RANGE <>) OF t_fft_sosi_out;

All constants used to define the ranges of the field in the types are defined prior and in the same file. This type is used everywhere in my code as an interface and works well.

Now I have this function:

FUNCTION func_dp_stream_arr_combine_data_info_ctrl(dp : t_fft_sosi_arr_out; info, ctrl : t_fft_sosi_out) RETURN t_fft_sosi_arr_out IS
VARIABLE v_dp : t_fft_sosi_arr_out(dp'RANGE) := dp;       -- hold sosi data
BEGIN
FOR I IN dp'RANGE LOOP                          -- set sosi info
  v_dp(I).bsn     := info.bsn;      
  v_dp(I).channel := info.channel;  
  v_dp(I).empty   := info.empty;    
  v_dp(I).err     := info.err;      
  -- set sosi ctrl
  v_dp(I).valid := ctrl.valid;
  v_dp(I).sop   := ctrl.sop;
  v_dp(I).eop   := ctrl.eop;
  v_dp(I).sync  := ctrl.sync;
END LOOP;
RETURN v_dp;
END func_dp_stream_arr_combine_data_info_ctrl;

that is meant to take an array of records and alter some of each records' fields (minus the re and im field) to be like that of the ctrl or info records provided.

At some point in my code I use the function as such:

nxt_src_out_arr <= func_dp_stream_arr_combine_data_info_ctrl(snk_in_arr, out_sosi, out_sosi);

and it completely messes up my re and im fields see here (sorry it is a little blurry):

snk_in_arr and nxt_src_out_arr are both ```t_fft_sosi_arr_out(g_nof_streams-1 DOWNTO 0);`` arrays where g_nof_streams is a defined generic. If I do not go via the function as such:

nxt_src_out_arr <= snk_in_arr;

Then the re and im fields match and all is well:

I'm running this on Vivado 2020.2 on Windows 10. I've found that this issue does not occur with Vivado 2020.1 (on Mint or Windows 10).

Thanks in advance.

Answer 1

I've found that this appears to be a version issue for both this problem and the one mentioned here.

As you can see, in Vivado 2020.1 (below) nxt_src_out_arr and snk_in_arr now match after running it through the function in question:

Thanks all, I'd log this issue with Vivado but I am struggling to do so. I've also logged in several times and filled in a survey in an attempt to reach the community forum. When I finally got there, I get errors when selecting 'Vivado' as my topic for my question. Hopefully they find this issue here.