Assign std_logic to a std_logic_vector entity port of size 1

Question

If I have an entity that has a dataport sig_i specified as follows

ENTITY input_sync IS
  GENERIC(
    signal_width : INTEGER := 1;
    synch_depth  : integer := 1
  );
  PORT(
    clk_i : IN  STD_LOGIC;
    rst_i : IN  STD_LOGIC;
    sig_i : IN  STD_LOGIC_VECTOR(signal_width - 1 DOWNTO 0);
    sig_o : OUT STD_LOGIC_VECTOR(signal_width - 1 DOWNTO 0)
  );
END input_sync;

and I specify the generic signal_width of this instance as 1 I end up with sig_i being

sig_i : in std_logic_vector(0 downto 0);

Is there a possibility to assign a normal std_logic to this port or do I always have to go the extra round of introducing an intermediate std_logic_vector for the assignment?

signal temp : std_logic_vector(0 downto 0);
signal data : std_logic;

temp(0) <= data;

u1 : input_sync
generic map(
  signal_width := 1
)
port map(
  ...
  sig_i => temp,
  ...
);

Answer 1

Array ports can be mapped element by element or slice by slice as long as once you start mapping you map all elements contiguously (not necessarily in order though).

u1 : input_sync
generic map(
  signal_width := 1
)
port map(
  ...
  sig_i(0) => data,
  ...
);