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makefiledependenciesgnu

Using dependencies in a GNU makefile

I am having a doubt on how to use dependencies in my GNU makefile.
Consider the following make file:

// Building all my dependency files
$(OUTDIR)/%.dep: %.c
    $(DPP) $(CPPFLAGS) $(DPPFLAGS) $(@:dep=o) $< $@

Now, I have these dependency files containing lists or "pointer" to files/dependencies.

I then want to create my object files based on those dependencies (when they change).
Can I do the following thing:

$(OUTDIR)/%.o $(OUTDIR)/%.orc: %.c $(OUTDIR)/%.dep
   $(AS) $(COMMONFLAGS) $(CPPFLAGS) $(ASFLAGS) -o $@ $<

Does that not however mean that I will be rebuilding my objects only when my *.dep files actually change (not the files listed within those dependency files). Is that the correct way of doing it? If not, what is?
I feel like I am not using/understanding how these dependency files are being interpreted by the tools.

Solution

  • The dependency files are themselves in makefile format, and is input to make, not gcc. To use them, you will need to include them in your makefile (ignoring the file if it hasn't been created yet):

    -include $(wildcard *.dep)

    The only caveat is that it will then build the dep files whenever it needs to build anything, including a "make clean", so you need to make the include conditional on the target:

    ifneq ($(MAKECMDGOALS),clean)
-include $(wildcard *.dep)
endif