There are ARM64 registers like S3_0_C12_C12_1 defined in ATF code (ARM trusted firmware)
/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
#define ICC_SGI1R S3_0_C12_C11_5
#define ICC_SRE_EL1 S3_0_C12_C12_5
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_SRE_EL3 S3_6_C12_C12_5
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
#define ICC_RPR_EL1 S3_0_C12_C11_3
#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
But I am not able find any document about these S3_0_C4_C6_0 definitions. Does anybody know the information of them? Thank you very much.
The latest official list of System Registers and their detailed descriptions is available on the Exploration Tools page of the ARM WEB site.
ICV_IGRPEN1_EL1 is recognized for example by GNU AS as s3_0_c12_c12_7 because
the values specified in the ARM documentation for op0, op1, CRn, CRm and op2 are:
op0 op1 CRn CRm op2
0b11 0b000 0b1100 0b1100 0b111
Once converted in decimal:
3 0 12 12 7
Bottom line, official names for the registers you are mentioning are:
ICC_CTLR_EL1 (s3_0_c12_c12_4)
ICC_CTLR_EL3 (s3_6_c12_c12_4)
ICC_IGRPEN0_EL1 (s3_0_c12_c12_6)
ICC_IGRPEN1_EL1 (s3_0_c12_c12_7)
ICC_IGRPEN1_EL3 (s3_6_c12_c12_7)
ICC_PMR_EL1 (s3_0_c4_c6_0)
ICC_RPR_EL1 (s3_0_c12_c11_3)
ICC_SGI1R_EL1 (s3_0_c12_c11_5)
ICC_SRE_EL1 (s3_0_c12_c12_5)
ICC_SRE_EL2 (s3_4_c12_c9_5)
ICC_SRE_EL3 (s3_6_c12_c12_5)
ICV_CTLR_EL1 (s3_0_c12_c12_4)
ICV_IGRPEN0_EL1 (s3_0_c12_c12_6)
ICV_IGRPEN1_EL1 (s3_0_c12_c12_7)
ICV_PMR_EL1 (s3_0_c4_c6_0)
ICV_RPR_EL1 (s3_0_c12_c11_3)