I'm getting an syntax error in my VHDL code near counter

Question

I'm trying to simulate a pulse width modulate (PMW) waveform generator and getting a syntax error in ISE. Checked fuse.xmsgs and found out it's near counter. Can someone point out the syntax error, please?

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity pwm_gen is
    port
    (
        clock, reset : in std_logic;
        width       : in std_logic_vector(7 downto 0);
        pwm          : out std_logic);
end pwm_gen;

architecture bhv of pwm_gen is
    type counter is range 0 to 255; 
    counter count := 0; 
begin
    process (clock) 
    begin
        if (reset = '1') then 
            count <= 0;
        elsif (clock'event and clock = '1') then 
            if (count <= width) then
                count <= count + 1; 
                pwm <= '1';
            else
                count <= count + 1; 
                pwm <= '0';
            end if;
        end if;
    end process;
end bhv;

Answer 1

counter count := 0;

This is illegal syntax, as you didnt declare the object class (signal, constant, variable). You need to use the format:

signal count : counter := 0

This is also illegal, as you are comparing an integer to a std_logic_vector that you havent included a package for. You need to convert the slv to an unsigned

if (count <= unsigned(width)) then

And finally, reset is missing from the sensitivity list