STD_LOGIC_VECTOR does not match integer literal

I am very very new to VHDL, and i am trying to write this code that the process is driving the output vector HEX0 depending on the inputs SW. this is what i have so far.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
    port (SW : in std_logic_vector (3 downto 0);
        LEDR : out std_logic_vector (3 downto 0);
        HEX0 : out std_logic_vector (6 downto 0));
end entity;

architecture top_arch of top is
    begin
        LEDR <= SW;
            -- Decoder process goes here…
            process (SW)
                begin
                    if  (SW = "0000") then
                        HEX0 <= (100000);
                    elsif   (SW = "0001") then
                        HEX0 <= (100111);
                    end if;
        end process;
end architecture;

and this is the error message

10517 HVDL type mismatch error at top.vhd(17): std_logic_vector type does not match integer literal

I am very new to this so I have no idea why this is happening. please let me know your thoughts. thank you.

Solution

In the lines HEX0 <= (100000); and HEX0 <= (100111); the numbers are interpreted as the integer number 100000 and 100111, and not a bitwise series of ones-and-zeros.

It's complaining that you are trying to assign an integer to a std_logic_vector type signal - which is not allowed.

To use std_logic_vector literals you'd write: HEX0 <= "100000"; and HEX0 <= "100111";