t_tone_array type does not match string literal

Question

i want to set all vectors 9 downto 1 in the array to "0000000", but i get the error message: Error (10515): VHDL type mismatch error at melody_box.vhd(251): t_tone_array type does not match string literal

type t_tone_array is array (0 to 9) of std_logic_vector(6 downto 0) ;

note_vector : out t_tone_array;

output : process(all)
    begin
    
    note_vector(9 downto 1) <= "0000000";  **--here is the error**
    
    if( button_6 = '0') then 
    note_vector(0) <= std_logic_vector(to_unsigned(melody_note_0(indexx-1),7));
    velocity(0 to 9) <= "1111111";
    
    elsif (button_6 = '1') then
    note_vector(0) <= std_logic_vector(to_unsigned(melody_note_1(indexx-1),7));
    velocity(0 to 9) <= "1111111";
    
    end if;
    end process output;

Does someone has an idea what's the problem?

Answer 1

A Minimal, Complete, and Verifiable example would look something like:

library ieee;
use ieee.std_logic_1164.all;

entity t_tone is -- Minimal, Complete, and Verifiable example
end entity;

architecture mcve of t_tone is
    type t_tone_array is array (0 to 9) of std_logic_vector(6 downto 0) ;
    signal note_vector: t_tone_array;
begin
    process
    begin
        note_vector(9 downto 1) <= "0000000";
        wait;
    end process;
end architecture;

which when analyzed (compiled) exhibits two errors:

ghdl -a t_tone.vhdl
t_tone.vhdl:13:20:error: direction of the range mismatch
        note_vector(9 downto 1) <= "0000000";
                   ^
t_tone.vhdl:13:36:error: can't match string literal with type anonymous array subtype defined at t_tone.vhdl:13:21
        note_vector(9 downto 1) <= "0000000";
                                   ^
ghdl:error: compilation error

A null slice (the direction incorrect) has no elements.

Correcting those requires getting the slice direction the correct way and providing a value of the type of the assignment target:

architecture fixed of t_tone is
    type t_tone_array is array (0 to 9) of std_logic_vector(6 downto 0) ;
    signal note_vector: t_tone_array;
begin
    process
    begin
        note_vector(1 to 9) <= (others =>"0000000");
         wait;
    wait;
    end process;
end architecture;

This analyzes and elaborates (compiles, links and loads) and simulates. The waveform expression on the right hand side is an aggregate which takes it's type from context (the entire assignment statement). This example will work with a tool compliant with revision -2008 of the VHDL standard.