Why are you giving an error in "=" in my VHDL code

Question

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY f_4fir_cont IS
    PORT (
        rst, clk : IN std_logic;
        ctrl : OUT std_logic
    );
END f_4fir_cont;
ARCHITECTURE bhvrl OF f_4fir_cont IS TYPE state_enum IS (s0, s1);
    SIGNAL state : state_enum := s0;
    SIGNAL nexts : state_enum := s1;

BEGIN
    clkp : PROCESS (clk, rst)
    BEGIN
        IF (rst = "0") THEN
            state <= s0;
        ELSIF (clk'EVENT AND clk = "1" AND
            clk'LAST_VALUE = "0") THEN
            state <= nexts;
        END IF;
    END PROCESS clkp;

    transp : PROCESS (state)

    BEGIN
        CASE state IS
            WHEN s0 => nexts <= s1;
            ctrl <= "0";
            WHEN s1 => nexts <= s0;
            ctrl <= "1";
        END CASE;
    END PROCESS transp;
END bhvrl;

I found this code in a book and am giving this error IF (rst = "0") THEN: Error (10327): VHDL error at f_4fir_cont.vhd(17): can't determine definition of operator ""="" -- found 0 I have already researched and found nothing to solve, I am starting in VHDL and I need help.

Answer 1

Both rst and clk are std_logic, which is an enumerated type. You are comparing them to arrays. Change all of the compares to single characters:

if rst = '0' then

etc.