I am getting this vsim error when I'm trying to use an Intel On-Chip Flash IP generated by Quartus. There's an altera_onchip_flash_block.v file in the submodules/rtl folder but it's only hex numbers in it so it's not compilable by ModelSim.
# Time: 0 ps Iteration: 0 Instance: /ufm_testbench/ufm_inst/flash/onchip_flash_0 File: ../../FFB900_UFM/verilog/altera_onchip_flash.v Line: 309
# Searched libraries:
(all my libraries)
The altera_onchip_flash_block gets instantiated in the altera_onchip_flash.v as seen above. When I'm only compiling the IP it's working but when I'm using it from my Top-Level testbench I always get this error. I am using VHDL in all my files, except the verilog files generated by quartus.
Any help is appreciated.
As you already realized, this is a precompiled IP-Core. Normally these precompiled IP-Cores come with files for simulation.
This pdf includes a step-by-step tutorial to instantiate the IP-Core and generate simulation files with Quartus (on page 12 of 36 or section 4-2).