How to assign a row in 2D Net in Verilog?

Question

I have a 2D wire, and I am trying to assign one of its rows to a temporary wire of the same length. For some reason, in the simulation, the temporary wire doesn't take those values.

generate
    for(i=16;i<64;i=i+1) begin
    assign temp[31:0] = w[i-15];
    assign s0 = {temp[6:0],temp[31:7]} ^ {temp[17:0],temp[31:18]} ^ {temp[2:0],temp[31:3]};
    assign s1 = {temp[16:0],temp[31:17]} ^ {temp[18:0],temp[31:19]} ^ {temp[9:0],temp[31:10]};
    assign out[i] = w[i-16] + s0 + w[i-7] + s1;
    end
endgenerate

Here, the variable 'temp' is expected to take the values of a row of variable 'w' each time, but during simulation, 'temp' is always having 32'hzzzzz... value.

This is the complete code

module message_scheduler(chunk_512, out);
input [31:0]chunk_512[15:0];
output [31:0]out[63:0];
wire[31:0]w[63:0];
wire[31:0]temp,s0,s1;
genvar i;
generate
    for(i=0;i<16;i=i+1) begin
        assign w[i] = chunk_512[i];
    end
    for(i=16;i<64;i=i+1) begin
        assign w[i] = 32'b0;
    end
endgenerate
generate
    for(i=16;i<64;i=i+1) begin
    assign temp[31:0] = w[i-15];
    assign s0 = {temp[6:0],temp[31:7]} ^ {temp[17:0],temp[31:18]} ^ {temp[2:0],temp[31:3]};
    assign s1 = {temp[16:0],temp[31:17]} ^ {temp[18:0],temp[31:19]} ^ {temp[9:0],temp[31:10]};
    assign out[i] = w[i-16] + s0 + w[i-7] + s1;
    end
endgenerate   
endmodule

Can someone please help me figure out where I am going wrong?

These are the commands I used to provide the input

force -freeze {sim:/message_scheduler/chunk_512[1]} {32'b01101111001000000111011101101111}
    force -freeze {sim:/message_scheduler/chunk_512[2]} {32'b01110010011011000110010010000000}
    force -freeze {sim:/message_scheduler/chunk_512[0]} {32'b01101000011001010110110001101100}
    force -freeze {sim:/message_scheduler/chunk_512[3]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[4]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[5]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[6]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[7]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[8]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[9]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[10]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[11]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[12]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[13]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[14]} 32'b00000000000000000000000000000000
    force -freeze {sim:/message_scheduler/chunk_512[15]} 32'b00000000000000000000000001011000

Answer 1

I get a warning when I compile your module:

    assign temp[31:0] = chunk_512[i-15];
                                |
xmelab: *W,BNDMEM : Memory index out of declared bounds.

You declared chunk_512 to have 16 locations (0-15), but you are trying to access locations 16 and above. This is the reason temp does not have known values.

For example, when the for loop reaches i=31, 31-15=16, so [16] is out of bounds.

---

Also, 2D ports require you to enable SystemVerilog features in your simulator.