While trying to understand the timer work, I wondered why the APB's peripheral clock was not followed and used by multiplying double.
Is this a phenomenon caused by a structural problem? Or is it a part that is handled automatically for convenience?
Can you tell me the answer and associated STMicroelectronics document for reference?
The timer clock is able to be set higher than the APB clock to allow power saving by reducing APB frequency while still achieving high timer resolution.
The details are in the reference manual. For STM32F427-439 pay attention to the TIMPRE bit in the RCC_DCKCFGR register, and see figure 16 "clock tree" in manual RM0090.