fpgaxilinxspartan
"logical root block and symbol is not supported in target" error in ISE Design Suite 14.7
I'm a total noob in ISE Design Suite 14.7 and I don't know a thing. I'm trying to make a SR latch (I know there is a SR latch in ISE but I want to create it myself to practice). the SR latch itself works fine but I get an error from Top_Module. here is the code for SR latch:
and the top module code and the error when I want to implement it:
It works fine when I change the top module to SRlatch.v and not the topmodule.v. what should I do? please don't say I have to search on google because I don't understand a thing.
Solution
I solved the problem. What I wrote was rudimentary and also wasn't well connected and it couldn't implement it. But I wanted to see the result by using ModelSim and it was fine with it and compiled it.
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