So I am trying to write the VHDL for a 32-bit ALU on EDA PLayground, but I get some error messages that I don't quite get, and I don't know how to fix them, can someone please help? I cannot understand where the mistakes are, and I don't know what to change in my code to fix them.
The following is the VHDL code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.ALL;
entity alu is
port(
A, B: in std_logic_vector(31 downto 0);
opcode: in std_logic_vector(2 downto 0);
Result: in std_logic_vector(31 downto 0)
);
end entity alu;
architecture dataoperations of alu is
begin
Result <= A + B when opcode="1010"
else A - B when opcode="1000"
else abs(A) when opcode="1011"
else -A when opcode="1101"
else abs(B) when opcode="0001"
else -B when opcode="1001"
else A or B when opcode="0110"
else not A when opcode="1111"
else not B when opcode="0101"
else A and B when opcode="1100"
else A xor B when opcode="0010";
end architecture dataoperations;
Here is the testbench code:
library IEEE;
use IEEE.std_logic_1164.all;
entity mytestbench is
end entity mytestbench;
architecture test of mytestbench is
signal in1, in2, out1: std_logic_vector (31 downto 0);
signal in3: std_logic_vector (2 downto 0);
begin
g1: entity work.alu(dataoperations)
port map (A <= in1, B <= in2; opcode <= in3, Result <= out1);
in1 <= "0001", "0FAF" after 20 ns, "F000" after 40 ns;
in2 <= "0100", "7FFF" after 10 ns, "FFFF" after 30 ns;
in3 <= "00";
end architecture test;
And here are the error messages:
COMP96 File: design.vhd
COMP96 Compile Architecture "dataoperations" of Entity "alu"
COMP96 ERROR COMP96_0143: "Object "Result" cannot be written." "design.vhd" 15 2
COMP96 File: testbench.vhd
COMP96 ERROR COMP96_0724: "',' or ')' expected." "testbench.vhd" 12 28
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 12 31
COMP96 ERROR COMP96_0019: "Keyword 'when' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0019: "Keyword 'end' expected." "testbench.vhd" 12 65
COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 12 66
COMP96 ERROR COMP96_0019: "Keyword 'of' expected." "testbench.vhd" 16 22
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 16 22
The last 8 errors are a semicolon used where a comma separator should be in the g1 port map.
-- port map (A <= in1, B <= in2; opcode <= in3, Result <= out1);
port map (A => in1, B => in2, opcode => in3, Result => out1);
A list is separated by commas, except a list of interface declarations which are separated by semicolons. This is a lost of port associations in a port map aspect (which isn't a declaration, while a port clause is).
(NOTE port map associations use the compound delimiter => and not <= between the formal port and actual signal. This would have been another dozen or so errors.)
The first error is because the alu port Result has the wrong mode (should be mode out).
These are typographic errors.
There are as yet undisclosed errors in mytestbench.
The string values assigned to in1, in2 should be bit strings (e.g. x"7FFF") where hex digits represent 4 elements each, and you show 16 elements when there should be 32 (e.g. x"00007FFF"). The value assigned to in3 doesn't have enough elements. As poor examples:
-- in1 <= "0001", "0FAF" after 20 ns, "F000" after 40 ns;
-- in2 <= "0100", "7FFF" after 10 ns, "FFFF" after 30 ns;
-- in3 <= "00";
in1 <= x"00000001", x"00000FAF" after 20 ns, x"0000F000" after 40 ns;
in2 <= x"00000100", x"00007FFF" after 10 ns, x"0000FFFF" after 30 ns;
in3 <= "000";
It isn't a bad first effort. The volume of errors from the semicolon where a comma is expected is surprising and reflects on the parser architecture found in ALDEC's tool. A parser with a lookahead of 1 would have (should have) quit sooner. Syntax errors can be hard to provide useful error messages for, they are detected before any semantic analysis. Your last recourse may be in examining the syntax (described in the LRM, IEEE Standard 1076).
The first error on the same line:
OMP96 ERROR COMP96_0724: "',' or ')' expected." "testbench.vhd" 12 28
where the last two numbers are line number and character position is the one needing attention first. You'd almost think quitting after the first error would be better to 'teach' you the language syntax.
There's also an undisclosed simulation error where for example when opcode="1010" has a mismatch between the string literal length and number of elements in opcode (3, 2 downto 0). The equality operator will always evaluate to FALSE. Either fix the string literals or have a matching number of elements in opcode.