I am looking at this:
Architecture characteristic key
-----------------------------------------------------------------------
H A hardware implementation does not exist.
M A hardware implementation is not currently being manufactured.
S A Free simulator does not exist.
L Integer registers are narrower than 32 bits.
Q Integer registers are at least 64 bits wide.
N Memory is not byte addressable, and/or bytes are not eight bits.
F Floating point arithmetic is not included in the instruction set
I Architecture does not use IEEE format floating point numbers
C Architecture does not have a single condition code register.
B Architecture has delay slots.
D Architecture has a stack that grows upward.
l Port cannot use ILP32 mode integer arithmetic.
q Port can use LP64 mode integer arithmetic.
r Port can switch between ILP32 and LP64 at runtime.
(Not necessarily supported by all subtargets.)
c Port uses cc0.
p Port uses define_peephole (as opposed to define_peephole2).
b Port uses '"* ..."' notation for output template code.
f Port does not define prologue and/or epilogue RTL expanders.
m Port does not use define_constants.
g Port does not define TARGET_ASM_FUNCTION_(PRO|EPI)LOGUE.
i Port generates multiple inheritance thunks using
TARGET_ASM_OUTPUT_MI(_VCALL)_THUNK.
a Port uses LRA (by default, i.e. unless overridden by a switch).
t All insns either produce exactly one assembly instruction, or
trigger a define_split.
e <arch>-elf is not a supported target.
s <arch>-elf is the correct target to use with the simulator
in /cvs/src.
| Characteristics
Target | HMSLQNFICBD lqrcpbfmgiates
-----------+---------------------------
aarch64 | Q q b gia s
alpha | ? Q C q mgi e
arc | B b gia
arm | b ia s
avr | L FI l cp g
bfin | F gi
c6x | S CB gi
cr16 | L F C c g s
cris | F B gi s
csky | b ia
epiphany | C gi s
fr30 | ?? FI B pb mg s
frv | ?? B b i s
gcn | S C D q a e
h8300 | FI B g s
i386 | Q q b ia
ia64 | ? Q C qr b m i
iq2000 | ??? FICB b g t
lm32 | F g
m32c | L FI l b g s
m32r | FI b s
m68k | pb i
mcore | ? FI pb mg s
mep | F C b g t s
microblaze | CB i s
mips | Q CB qr ia s
mmix | HM Q C q i e
mn10300 | ?? gi s
moxie | F g t s
msp430 | L FI l b g s
nds32 | F C ia s
nios2 | C ia
nvptx | S Q C q mg e
pa | Q CBD qr b i e
pdp11 | L IC qr b e
powerpcspe | Q C qr pb ia
pru | L F a s
riscv | Q C qr gia
rl78 | L F l g s
rs6000 | Q C qr pb ia
rx | s
s390 | Q qr gia e
sh | Q CB qr p i
sparc | Q CB qr b ia
stormy16 | ???L FIC D l b i
tilegx | Q C q gi e
tilepro | S F C gi e
v850 | g a s
vax | M I b i e
visium | B g t s
xtensa | C
That looks like about 50 architectures. Where is all that implemented in the source code on GitHub? For GCC, clang, and/or LLVM (or any other key project that might be of interest in terms of implementing architecture integration).
For LLVM (Clang is frontend based on LLVM) you can find the backend codes for each architecture in llvm/lib/Target/ directory. LLVM use .td target description files to describe the targets (it is a language of its own). Like the instructions, the registers, calling conventions and such.
Also in these directories are the .cpp files too which implement certain functionalities. For example llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp file implement a pass to fill delay slots with useful instructions for Mips architecture.
There is this repository of git patches for adding RISC-V target, which is a nice example how to implement a backend incrementally. Also there is a lot of documentation, but keep in mind that it is quite outdated, but still has usefull informations.