I have to make an arbitrary counter for a determined sequence, and after making the transition table and the karnaugh maps, I was left with some equations that I turned into this Verilog program. It uses four JK bistable circuits.
However, when I execute, the program just prints 0's instead of the count I want, and I can't find why. I am sorry about the comments (I am Spanish).
//modulo del biestable JK
module biestableJK (output reg Q, output wire NQ, input wire J, input wire K, input wire C);
//hacemos Q negado, que es la salida secundaria del biestable JK
not(NQ,Q);
initial
begin
//inicializamos Q a 0
Q='b0;
end
//codificamos los biestables (por flanco de subida), y su modelo de comportamiento
always @(posedge C)
case ({J,K})
2'b10: Q='b1; //set
2'b01: Q='b0; //reset
2'b11: Q=~Q; //complemento
endcase
endmodule
//modulo del contador
module contador (inout wire [3:0] Q, input wire C);
//Declaramos arrays de tipo wire para poder almacenar la informacion que sale del llamamiento a los modulos de biestable
wire [3:0] QNEG; //salidas negadas
wire [3:0] J; // entradas J
wire [3:0] K; //entradas K
//J3
wire wireAND1J3, wireAND2J3;
//K3
wire wireAND1K3, wireAND2K3;
//K1
wire wireAND1K1, wireAND2K1;
//J3
and andJ3 (J[3], Q[0], QNEG[1]);
//K3
and andK3 (K[3], Q[0], Q[1]);
//J2 y K2
and andJK2 (J[2], Q[0], Q[1], Q[3]);
//J1
or orJ1 (J[1], Q[0], Q[3]);
//K1
and and1K1 (wireAND1K1, QNEG[0], QNEG[3]);
and and2K1 (wireAND2K1, QNEG[2], QNEG[3]);
and and3K1 (wireAND3K1, Q[0], Q[2], Q[3]);
or orK1 (K[1], wireAND1K1, wireAND2K1, wireAND3K1);
//J0 y K0
and and1JK0 (wireAND1JK0, QNEG[1], QNEG[3]);
and and2JK0 (wireAND2JK0, Q[1], Q[3]);
and and3JK0 (wireAND3JK0, Q[1], Q[2]);
or orJK0 (J[0], wireAND1J0, wireAND2J0, wireAND3J0);
biestableJK JK3 (Q[3], QNEG[3], J[3], K[3], C);
biestableJK JK2 (Q[2], QNEG[2], J[2], J[2], C);
biestableJK JK1 (Q[1], QNEG[1], J[1], K[1], C);
biestableJK JK0 (Q[0], QNEG[0], J[0], J[0], C);
initial
begin
end
endmodule
//modulo de test
module test;
wire [3:0] Q; //salidas de los biestables
reg C; //reloj
//llamada al modulo del contador (llamada al modulo) (nombre) (salidas Q, reloj)
contador CONT (Q,C);
//generamos elreloj: negamos C continuamente
always #10 C=~C;
//instrucciones para la ejecucion del modulo test
initial
begin
//declaramos la monitorizacion del cronograma y creamos
$dumpfile("cronograma.dmp");
$dumpvars(1,CONT);
$dumpon;
C='b0;
//sacamos por pantalla los resultados
$monitor($time, " C=%b | Q=%d| Q=%b%b%b%b \n",C,Q,Q[3],Q[2],Q[1],Q[0]);
//finalizamos la ejecucion a los 160 tics (hay 8 numeros y vamos a 10 tics por numero, asique hacemos dos ciclos)
#160 $finish;
//se finaliza el cronograma
$dumpoff;
end
endmodule
When I ran your simulation using Cadence's simulator, I got compile warnings like this:
or orJK0 (J[0], wireAND1J0, wireAND2J0, wireAND3J0);
|
xmelab: *W,CSINFI : implicit wire has no fanin (test.CONT.wireAND3J0).
I got 1 warning for each "wireAND" signal in that line. This means that you did not declare the wireAND3J0
signal, which means that its value is Z
.
Change:
or orJK0 (J[0], wireAND1J0, wireAND2J0, wireAND3J0);
to:
or orJK0 (J[0], wireAND1JK0, wireAND2JK0, wireAND3JK0);
Now, I get this output where Q
is changing:
0 C=0 | Q= 0| Q=0000
10 C=1 | Q= 1| Q=0001
20 C=0 | Q= 1| Q=0001
30 C=1 | Q=10| Q=1010
40 C=0 | Q=10| Q=1010
50 C=1 | Q=11| Q=1011
60 C=0 | Q=11| Q=1011
70 C=1 | Q= 6| Q=0110
80 C=0 | Q= 6| Q=0110
90 C=1 | Q= 5| Q=0101
100 C=0 | Q= 5| Q=0101
110 C=1 | Q=14| Q=1110
120 C=0 | Q=14| Q=1110
130 C=1 | Q=15| Q=1111
140 C=0 | Q=15| Q=1111
150 C=1 | Q= 0| Q=0000
You can use simulators on edaplayground which might give you helpful messages like the one I showed.
If you use $dumpvars;
(without arguments), you will get all signals in all modules in your VCD file. I used that to see that J
was unknown (X
) inside the biestableJK
module.