16bit multiplier vhdl code synthesize error

Question

I want to write a 16bit * 16bit multiplication code. Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mul is
   port
   (
      A, B: IN INTEGER RANGE -32768 TO 32767;

      C: OUT INTEGER RANGE -2147483648 TO +2147483647
   );
end mul;

architecture Behavioral of mul is
begin

   C <= A * B;

end behavioral;

But when I'm trying to sythesize the code on xilinx isim I get this error:

ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.

Answer 1

All the ports defined in the entity should have a pin assignment defined using ucf file. If you are missing an ucf file, the tool will go ahead and place the pins by itself. This is clearly stated in the error message.

NET"A(0)"                LOC ="AB16"       | IOSTANDARD ="LVTTL";
NET"A(1)"                LOC ="AB16"       | IOSTANDARD ="LVTTL";
...

In your example, the width of A & B is 16 bits and C is 32 bits. So you need to assign correct pin location and IO standard for all of them.