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vhdlendiannesssigned

vhdl signed and unsigned type endianess

I am writing a code in vhdl quite full of algebraic operations and I declared some signed variables (I know that there are better types, but I needed to reduce the bits used). I was wondering if it is better to declare them as

variable foo1 := signed (7 downto 0);

or

variable foo2 := signed (0 to 7);

I know it is related to endianess, but I am fairly confused. For example, if I declare

variable foo3 := signed (0 to 7) := "01100100";

Will it be interpreted as 100 or 38 in decimal? And if I have a condition on foo3 as

if (foo3(1) = '1') then
-- whatever you want
endif;

Will foo3(1) = '1' be true or false?

Solution

  • For consistency across VHDL's math packages, it is better to use downto.

    variable foo1 : signed (7 downto 0);

    This has nothing to do with numeric_std package. As with the numeric_std package, the leftmost element is always the most significant element, independent of whether you use downto or to. Also interesting with numeric_std, the value is in no way dependent on the indices - so (15 downto 8) works the same as (7 downto 0).

    On the other hand, with VHDL-2008's fixed point and floating point packages, the only direction supported is downto. The actual range has meaning. With fixed point, the indices have weight. Negative indices are the fractional part.

    variable foo4 : sfixed(7 downto -2) ; -- 8 bits of integer, 2 bits of fraction
variable foo5 : sfixed(7 downto 1) ; -- even numbers only.

    For more on fixed and floating point, see: https://synthworks.com/papers/vhdl_fixedfloat_lewis_bishop_date_2007.pdf

    For more on unsigned / signed, see:
    https://synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf