aarch64 use str/ldr to store/load register into memory:
str q0, [dst]
str x0, x1, [dst]
In the example above, q0/q1 is 128bit, as well as x1/x0 is 64bit, but how does str/ldp knows the the size of current register? is it related with word size?
In asm source, the register name implies the size.
In machine code, the opcode implies the size.
Exactly like str x0, [dst] vs. str w0, [dst] vs. strb w0, [dst]: all 3 assemble to different opcodes which imply different store sizes.
The fact that some of those opcodes share the str mnemonic while others have their own mnemonics is purely a matter of designing the asm source language, and irrelevant to how the CPU decodes and executes it.
(The choice is motivated by the lack of other instructions that treat a general-purpose register as 8 or 16 bits, like there are on x86. If you had a whole set of addb and shlb instructions, the designers of the assembly language might instead make up a byte register names like x0b or b0 or something and use those with mnemonics like add and str. Again, that would be somewhat like what x86 does for its "partial register" instructions. However, m68k has byte/word/long sizes for most instructions, and gets by just fine with add.b d1, d0 instead of needing to make up names for partial registers. Like ARM but unlike x86, m68k has no way to access the 2nd byte of a register like x86's AH, so that's probably the real factor that motivates x86's partial-register naming.)