VHDL state machines and clock

I have a general question about state machines used in VHDL. I heard that every state is processed in one clock cycle.

So lets say I have a state that needs more than one clock cycle to be finished. For example if I want to wait for a few seconds inside a state. Can this be done?

Or if I have a state in which I want to write to a blockram which needs 10 clock cycles (10 adresses) to be filled. Can this be done inside the case statements which are typically used for presenting state machines?

Solution

Usually in cases when you need to execute N repetitive actions in one state (like you described, waiting N ns, writting to N addresses.) it is often used a counter in it. Hope the following example may clarify it a bit:

process(clk, rst)
begin
if (rst = '1') then
index <= 0; -- memory address
current_s <= write_memory ;
currentValue <= (others => '0');
elsif rising_edge(clk) then
   case curresnt_s is 
   when write_memory =>
      if index < ADDRESS_SIZE then
        index <= index + 1; 
        memory(index) <= currentValue;
      else 
        curresnt_s  <= done;
      end if;
   when done => null;
   end case;
end case;

In this code memory would be an array of std_logic_vector; You could use the same idea to wait for 100ns. if you know your clock runs at 10ns period, you could count to 10 in some state before changing to other.