Applying simple inversion (NOT function) to OBUFDS

Question

I am a newbie here to ask a question, that is too easy for you to answer, but I am not familiar with.

I have "cabletester_prbs15_bytegenerator" IP in my BD, which has "data_out_p" and "data_out_n" connected to OBUFDS ports.

In my situation I have an OBUFDS connected to "data_out_p", but assign to NEGATIVE DIFFERENTIAL LEG in implementation. At the moment, after successful synthesis, when I try to assign it to IO_@@_N in synthesis design, It gives error message "cannot set LOC property of ports, the negative port (N-side) of a differential pair can not be placed on a positive Pin"

Long story short, I need to invert polarity of OBUFDS.

cabletester_prbs15_bytegenerator IP uses module "prbs15_bytegenerator" like below.

module cabletester_prbs15_bytegenerator_0_0 (
  clk,
  clk_div4,
  resetb,
  data_out_p,
  data_out_n
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetb:reset, FREQ_HZ 640000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN cabletester_clk_wiz_0_0_clk_320, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire clk_div4;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
input wire resetb;
output wire data_out_p;
output wire data_out_n;

  prbs15_bytegenerator inst (
    .clk(clk),
    .clk_div4(clk_div4),
    .resetb(resetb),
    .data_out_p(data_out_p),
    .data_out_n(data_out_n)
  );
endmodule

In prbs15_bytegenerator, you can see OBUFDS relevant part at the end

OSERDESE3  #(
      .DATA_WIDTH(8),
      .IS_CLKDIV_INVERTED(0),
      .IS_CLK_INVERTED(0),
      .IS_RST_INVERTED(1),
      .SIM_DEVICE("ULTRASCALE_PLUS")
      )
      oserdes_inst
    (
     .OQ(data_out),
     .CLK(clk),
     .CLKDIV(clk_div4),
     .D(prbsbyte),
     .RST(resetb)
     );
     
        OBUFDS outputbuf
     (
      .I(data_out),
      .O(data_out_p),
      .OB(data_out_n)
     );
endmodule

Is inverting the polarity just as simple as putting ~ in front of .O(data_out_p)? I would really appreciate if one could show what the code should exactly look like cuz I know very little about Verilog.....

Thank you so much....

Answer 1

You probably want to keep the polarity of the OBUFDS correctly orientated. P to positive leg, and N to negative leg. Instead, try invering the input to the OBUFDS by making the following tweak.

OBUFDS outputbuf
     (
      .I(~data_out),  // This will invert the input and cause the 
      .O(data_out_p), // output to logically invert.
      .OB(data_out_n)
     );