Automatically constrain string size using initialization in VHDL

Question

I'm working with VHDL, and I'm wondering if there is any way to constrain the string size when declaring it, using initialization. For example, we declare a string as follow:

variable sequence : string(1 to 20) := "AGTAACCAATTCGCATTCGC";

I would like to know if there is any way to do something like:

variable sequence : string := "AGTAACCAATTCGCATTCGC";

Of course, second line isn't valid, because interpreter says:

[VRFC 10-1547] variable cannot be unconstrained

Answer 1

Constants don't have to be constrained, so you could do this:

constant Csequence : string := "AGTAACCAATTCGCATTCGC";
variable Vsequence : string(Csequence'range) := Csequence;

---

https://www.edaplayground.com/x/r3wK

entity E is
end entity E;

architecture A of E is
begin
  process
    constant Csequence : string := "AGTAACCAATTCGCATTCGC";
    variable Vsequence : string(Csequence'range) := Csequence;
  begin
  wait;
  end process;
  
end architecture A;