Report throwing type mismatch error at elaboration

Question

I'm trying to debug some errors that are causing some variable width mismatch issues (the adding stage below).

To do this, I want to use report statements to output some variables used in the calculations of these variable widths.

However, for some reason, even the most simple report statement:

report "this is a message";

Is throwing this error:

syntax error near report

error type void does not match with a string literal

Any idea what could be causing this?

---

I'm using VHDL2008 in Xilinx Vivado.

The whole source file for reference:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.All;
use IEEE.math_real.all;
use work.functions.all;


entity averager is
    generic
    (
        buffer_len: positive := 32; -- MUST BE A POWER OF 2
        input_max: positive := integer'high / buffer_len -- Maximum value of one data input
    );
    port 
    (
        clk : in STD_LOGIC;
        tri : in STD_LOGIC; 
        reset: in std_logic;       
        data_in : in unsigned (get_min_counter_width(input_max) - 1 downto 0);
        avg_out : out unsigned (get_min_counter_width(input_max) - 1 downto 0)
     );
end averager;

architecture behavioral of averager is
    
    -- TODO - Add assert that buffer_len is power of 2


    constant input_width: positive := get_min_counter_width(input_max);
    constant accum_width: positive := get_min_counter_width(input_width * buffer_len); -- Done at synthesis time, perfomance non-critical
    constant avg_bitshift: positive := integer(ceil(log2(real(buffer_len)))); -- How much bitshift is needed for fast divide
    
    signal last_tri: std_logic := '0';
    
    subtype in_val is unsigned(input_width - 1 downto 0);
    type acc_buffer is array(buffer_len - 1 downto 0) of in_val;
    
    constant in_zero: in_val := to_unsigned(0,input_width);
    signal in_buffer: acc_buffer; -- Initialised in reset

    type state is (rst, idle, adding, writing);
    signal current_state: state := rst;
    signal next_state: state := rst;
    
    constant accum_zero: unsigned(accum_width - 1 downto 0) := to_unsigned(0,accum_width);
    signal accumulator: unsigned(accum_width - 1 downto 0) := accum_zero;
    

begin


    sync_proc: process(clk)
    begin
       if (rising_edge(clk)) then
           if (reset = '1') then
               last_tri <= '0';
                current_state <= rst;
            else
                last_tri <= tri;
                current_state <= next_state;
                if (last_tri = '0' and tri = '1') then
                    in_buffer <= in_buffer(in_buffer'high downto in_buffer'low + 1) & in_val(data_in);
                end if;
            end if;
        end if;
    end process;
    
    next_state_decode: process(current_state, tri)
    begin
       next_state <= current_state;
       case(current_state) is
           when rst =>
               next_state <= idle;
           when idle => 
               if (last_tri = '0' and tri = '1') then
                   next_state <= adding;
               end if;
           when adding =>
                   next_state <= writing;
           when writing =>
                   next_state <= idle;     
       end case;
    end process;
    
    output_decode: process(current_state)
    begin
       next_state <= current_state;
       case(current_state) is
           when rst =>
               next_state <= idle;
               for i in in_buffer'high downto 0 loop
                    in_buffer(i) <= in_zero;
               end loop;
           when idle => 

           when adding =>
               for i in in_buffer'high downto 0 loop
                    accumulator <= unsigned(accumulator) + resize(unsigned(in_buffer(i)),accum_width);
               end loop;
           when writing =>
                   avg_out <= accumulator(accumulator'high downto accumulator'low + avg_bitshift);     
       end case;
    end process;
    
    
    report "this is a message";
    


end behavioral;

Answer 1

A report statement is a sequential statement and can be used in sequential blocks only.

You can't use a report statement in architecture code, which is for concurrent statements only.

A report statement is a sequential statement by itself.

An assert statement can be used in concurrent blocks. The message in the report clause of the assertion will be printed if the assertion is false.

VHDL has a constant, false, of boolean type which has the value False. So if an assert false is used, the message in the report clause will be printed always.

So an assert false report "your message"; can also be used if you want to print a message in a concurrent block.