haskellcompiler-constructionllvmx86-64ghc

LLVM's calling convention for GHC


Here is the text in LLVM's doc "langref":

"cc 10" - GHC convention

This calling convention has been implemented specifically for use by the Glasgow Haskell Compiler (GHC). It passes everything in registers, going to extremes to achieve this by disabling callee save registers. This calling convention should not be used lightly but only for specific situations such as an alternative to the register pinning performance technique often used when implementing functional programming languages.At the moment only X86 supports this convention and it has the following limitations:

  • On X86-32 only supports up to 4 bit type parameters. No floating point types are supported.
  • On X86-64 only supports up to 10 bit type parameters and 6 floating point parameters.

Q:

  1. does "register pinning" means or refers to "passes everything in registers", likely.

  2. what is "4 bit type parameters"? I just searched in the Intel's IA manual, but didn't find anything. does it a feature of Intel's CPU?


Solution

    1. "Register pinning" seems to refer to assigning specific things to specific hardware registers; see the "Register Pinning" section of these GHC LLVM back-end notes and the linked discussion.

    2. Dirk is right - you can see it clearly in the LLVM tblgen code which defines these conventions (look for CC_X86_64_GHC and CC_X86_32_GHC).