VHDL compliling error Testbench (ModelSim)

Question

I am currently doing a project in ModelSim, and Im having some trouble with the compilation. All I want to is change the value of my pin from 0 to 1, but when I compile it says that there os a error. tool directives are not supported before VHDL 2008. I dont know why this is happening, once that my professor disponiblized a example file and I did exactly like he did. The full code is below.

-- João Vítor Abrantes - 19/0031085
-- UnB - Engenharia Elétrica 
--
--  - Experimento 2 -
--   Somador Completo

-- Entity 
entity testbench is end;

-- Library
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

architecture tb_sum of testbench is
-- Component
component tb_sum1
    port(
        W    : in  std_logic; --A
        X    : in  std_logic; --B
        Y    : in  std_logic; --Cin
        Z    : out std_logic; --S
        Z1   : out std_logic  --Cout
    );
end component;

    signal i_1 : std_logic;
    signal i_2 : std_logic;
    signal i_3 : std_logic; 

Begin

    S1    : tb_sum1 port map ( W => i_1 , Y => i_2 , X => i_3 , Z => open);
    Cout1 : tb_sum1 port map ( W => i_1 , Y => i_2 , X => i_3 , Z1 => open);

estimulo: process 

begin 

wait for 5 ns; i_1 <= `1`, -- This is the part that he says the error is
wait for 5 ns; 
wait for 5 ns; 
wait for 5 ns; 
wait for 5 ns; 
wait for 5 ns; 
wait for 5 ns; 
wait;
end process estimulo;

end tb_sum;

Answer 1

I searched for tool directives VHDL, and I get this:

Tool directives are arbitrary words preceded by a backtick character `.

I believe ' or " should be used here.