Evaluation of SystemVerilog assign statements in RTL simulation
I'm trying to understand why the statement coverage of two SystemVerilog assign statements could differ from each other when the condition expression is the same for both of the statements.
Consider the following:
As shown, the condition expression is same for these two statements, i.e., _T_6.
However, the number of hits (i.e., statement coverage) for the statements are different (notice the numbers on the far left).
I was expecting that RTL simulator should evaluate both statements equal number of times whenever the value of _T_6 changes. How does the RTL simulator handle these statements during simulation?
The continuous assignment statement gets evaluated anytime a signal on the right-hand-side changes. So even when _T_6 does not change, changes on the inactive branch of the conditional expression still cause an evaluation.
If _T_6 was a parameter and not a signal, there are some optimizations that might reduce the conditional expression and eliminate some evaluations.
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