Why opcode is 6-bit long in MIPS 32 bit Architecture

Question

Below is Data transfer instruction format for 32-bit ARM and MIPS architecture. 32-bit ARM architecture have 4 bit opcode because there are 16 registers (2^4=16).32-bit MIPS architecture have 6 bit opcode. Should not it be 5 bits considering there are 32 registers in MIPS?

Answer 1

The number of registers has nothing to do with the number of opcode bits, it's related to the number of supported instructions (which still isn't a hard limiting factor, considering techniques like instruction prefixes exist).

On the other hand, the operand bit count (Rs and Rd in your picture) are related to the number of registers (they are 5 bit because MIPS has 32 registers, 2^5 = 32).

So having 6 bits for the opcode means only that you are able to encode up to 2^6=64 different instructions which can be interpreted in a single decode cycle.