I have an unclear question that I need more clarification about it. when I store data type like integer 4 byte. then how the processor with the architecture of 64 bit reads or writes an integer with a size of 4byte as I know the processor reads/writes a word. is there any padding size here. I will be thankful for some clarifications about that because I can not understand how it works or maybe I miss some things that I must read more about it. is it differs from compiler to compiler or language to language? Thanks a lot.
as I know the processor reads/writes a word
Word-oriented CPUs can load/store in 64-bit chunks, but also narrower chunks. (Storing the low part of a register, or loading with zero-extension or sign-extension). Capability to do narrow stores is fairly essential for writing device drivers for most hardware, as well as for implementing efficiently sized integers that don't waste a huge amount of cache footprint, and for some kinds of string processing.
Some CPUs (like x86-64) are not really word-oriented at all, and have about the same efficiency for every operand-size. Although the default operand-size in x86-64 machine code is 32-bit.
All mainstream 64-bit architectures natively support 32-bit operand-size, including even DEC Alpha which was aggressively 64-bit and chose not to provide 8-bit or 16-bit loads/stores. (See Can modern x86 hardware not store a single byte to memory? for more details)
There might be some highly obscure 64-bit architecture where only 64-bit load/store is possible, but that seems unlikely. Also note that most modern 64-bit ISAs evolved out 32-bit ISAs.