VHDL enumerator relational operators

Question

I'm currently programming a system in VHDL, and I'm using an enumerator from another package called vnir, which is defined as such:

package vnir is
    type row_type_t is (ROW_NONE, ROW_NIR, ROW_BLUE, ROW_RED);
end package vnir;

I've defined my architecture as such

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.vnir;

entity imaging_buffer is
    port(
        clock           : in std_logic;
        reset_n         : in std_logic;
        vnir_row_ready  : in vnir.row_type_t
    );
end entity imaging_buffer;

architecture rtl of imaging_buffer is
    signal vnir_row_ready_i : vnir.row_type_t;
begin
    vnir_pipeline : process (reset_n, clock) is
    begin
        if (reset_n = '0') then
            vnir_row_ready_i <= vnir.ROW_NONE;
        elsif rising_edge(clock) then
            if (vnir_row_ready /= vnir.ROW_NONE) then
                --do stuff
            end if;
       end if;
    end process vnir_pipeline;
end architecture;

The internal signal vnir_row_ready_i can be assigned to no problem, however the relational operator doesn't seem to work as ModelSim throws this error when I try to compile:

# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): (vcom-1581) No feasible entries for infix operator '/='.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): Type error resolving infix expression "/=" as type std.STANDARD.BOOLEAN.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(28): VHDL Compiler exiting

Answer 1

My coworker helped me figure out how to make it work! I think that the /= operator is created in the vnir scope, but not ported over to the entity I'm working on. By writing :use work.vnir."/="; at the beginning of the file it compiles, so the full entity looks like so:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.vnir;
use work.vnir."/=";

entity imaging_buffer is
    port(
        clock           : in std_logic;
        reset_n         : in std_logic;
        vnir_row_ready  : in vnir.row_type_t
    );
end entity imaging_buffer;

architecture rtl of imaging_buffer is
    signal vnir_row_ready_i : vnir.row_type_t;
begin
    vnir_pipeline : process (reset_n, clock) is
    begin
        if (reset_n = '0') then
            vnir_row_ready_i <= vnir.ROW_NONE;
        elsif rising_edge(clock) then
            if (vnir_row_ready /= vnir.ROW_NONE) then
                --do stuff
            end if;
       end if;
    end process vnir_pipeline;
end architecture;

Alternatively it did work by including use work.vnir.all; and taking out the vnir. before the types, but that wasn't possible with the project I'm working one