how to reduce integer bit size in vivado

Question

I have to implementation my design to board nexys 4. In my design, I have 4 inputs with integer data types. The integer in vivado default has 32 bits data length, meanwhile in board nexys 4 only can process integer with maximum data length 16 bits to set in GPIO ports. so I want to know how can I reduce the data length of the integer from 32 bits to 16 bits, can you help me, please? Thank you

Answer 1

Use a standard vector type and convert it internally to integer:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_design is
port(
  v1, v2, v3, v4: in std_ulogic_vector(15 downto 0);
  ...
);
end entity my_design;

architecture rtl of my_design is
  signal i1, i2, i3, i4: natural range 0 to 2**16 - 1;
  ...
begin
  i1 <= to_integer(unsigned(v1));
  i2 <= to_integer(unsigned(v1));
  i3 <= to_integer(unsigned(v1));
  i4 <= to_integer(unsigned(v1));
  ...
  -- use signals i1, i2, i3, i4
  ...
end architecture rtl;

In case your integers are signed use:

  signal i1, i2, i3, i4: integer range -2**15 to 2**15 - 1;

and:

  i1 <= to_integer(signed(v1));