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yosysice40

Understanding logic tile LC_5 bits


i m new to yosys and arachne-pnr. Here is the snippet from .asc and .icebox_explain. I could not understand how the bits of LC_5 are derived from .logic_tile 1 11.

example.v

module top (input a, b, output y);
  assign y = a & b;
endmodule

example.asc

.logic_tile 1 11
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000001000000000000000000000000000000000000000
    000000000000000101000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000011000110000000000000000
    000000000000000000000000000000001110110000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000001111000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000
    000000000000000000000000000000000000000000000000000000

icebox_example.asc

   .logic_tile 1 11
LC_5 0000000000001111 0000
buffer local_g0_4 lutff_5/in_3
buffer local_g3_0 lutff_5/in_2
buffer neigh_op_lft_4 local_g0_4
buffer sp4_h_r_24 local_g3_0

How, LC_5 0000000000001111 0000 is generated from this stream?

Given in documentation:
LC_5 B10[36] B10[37] B10[38] B10[39] B10[40] B10[41] B10[42] B10[43] B10[44] B10[45] B11[36] B11[37] B11[38] B11[39] B11[40] B11[41] B11[42] B11[43] B11[44] B11[45]

I guess it should be:

B10-36:45=1100000000
B11-36:45=1100000000

which is not correct. Can you please help and guide?


Solution

  • LC_5 isn't the LC_ bits directly, but the 16 LUT init bits followed by 4 flipflop config bits.

    The mapping from these to LC_ bit index is another step, also described in http://www.clifford.at/icestorm/logic_tile.html right at the bottom.