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How to access the ISA configuration space and what does it look like?

How do you access the ISA configuration space programmatically and what does it look like -- how do you set base addresses for ISA PnP Option ROMs?

Solution

  • A card is selected using the ISA Isolation procedure as follows:

    On power up, all Plug and Play cards detect the ISA bus reset signal, RESET_DRV, set their CSN to 0, and enter the Wait for Key state. The software must delay 2 msec after RESET_DRV before accessing the auto-configuration ports (address, read, write), this is so that the device can perform initial configuration, load initial configuration register values from non-volatile memory, set CSN to 0 and enter the wait for key state in time. Cards in the Wait for Key state do not respond to any access to their auto-configuration ports until the initiation key is detected and will ignore all ISA accesses to their Plug and Play interface.

    The initiation key is sent by software by writing the sequence 6A,B5,DA,ED,F6,FB,7D,BE, DF,6F,37,1B,0D,86,C3,61 B0,58,2C,16,8B,45,A2,D1, E8,74,3A,9D,CE,E7,73,39 to the address port. When the ISA cards detect this sequence, they enter the sleep state. In this state, the cards listen for a Wake[CSN] command with the write data set to 0x00 by software. This Wake[CSN] command will send all cards to the Isolation state and entering this state it resets the serial identifier/resource data pointer to the beginning.

    The first time the cards enter the Isolation state it is necessary to set the READ_DATA port address using the Set RD_DATA port command (which is sent when you send an offset of 00h to the address port). Next, 72 pairs of reads are performed by software to the Serial Isolation register to isolate a card (offset 01h).

    A read causes each card to place 55h on SDL[7:0] if the next bit of their serial identification number is 1. If it isn't 1 then it asserts nothing and checks SDL[1:0] which will be 01 if 55h has been asserted by another card. If it's 01b then it will assert AAh next read, if not 01b it will check for 10b next read. The next read from the isolation register by software causes the cards that asserted 55h or that did not detect 01b to assert AAh. The other cards check the lower 2 SDL bits for 01b. If 01b is present, they enter a sleep state. All other cards check if they've sent the final bit of the serial identifier, if not, they move to the next round. If they have, it will be the only card remaining.

    enter image description here

    The isolated card remains in the Isolation state while all other cards have failed the isolation protocol and have returned to the Sleep state.

    Writes to the card control registers are intercepted by all devices in a sleep/isolation/config state and are interpreted as certain commands based on the data and what state they are in. A write to the wake register will be accepted by the card in the isolation state as the new CSN. The CSN on this card is set to a unique number. Writing this value causes this card to transition to the Config state. You then select a logical device number by writing to the LDN register, which only the device in Config state responds to by mapping the registers of that logical device below offset 0x30.

    The configuration space looks like this:

    enter image description here

    enter image description here

    In order to select a base address for a MMIO space (including Option ROM), you put a base address in a memory descptor at offset 0x40–0x5F. Presumably the upper limit register is written by the card to tell you how much memory it requires. On PCI, you write all 1s to the BAR to get the size. Not sure about ISA. There are 4 memory descriptors and 8 I/O descriptors. You configure a 24 bit address that resides somewhere in the 1MiB ISA hole below 16MiB that is programmed to be forwarded to the ISA Bridge.

    In order to continue the isolation procedure to isolate the next card, A Wake[CSN] command with a parameter of zero (write to the Wake register offset 0x03) will force all cards without a CSN to enter the Isolation state (a Wake[CSN] command with a parameter other than zero will force a card with a matching CSN to enter the config state. Any card that is in an isolation or Config state that receives a CSN that is not it's own transitions to the Sleep state).

    Don't forget that the ISA-XT bus appeared on 8086–80186 as an 8 bit bus with 20 bit addressing. 80286 chipsets and onwards it was 16 bit with 24 bit addressing. The 80486 SIO(.A) and IB southbridges were just single function PCI devices on the PCI bus that functioned as an ISA bridge. So was the PCEB southbridge (where the ESC subsouthbridge registers were accessed through IO ports). The PIIX–PIIX4E southbridges were multifunction PCI devices. The ICH0 southbridge was a multidevice and multifunction PCI device and the ISA bridge was an optional separate device on the PCI bus, separate to the southbridge.