L2 cache memory

What's the difference between 2*512 KB L2 cache and 1 MB L2 cache?

Solution

First one could be dedicated for dual core, 512 KB each core and the second could be shared, if more than one core?

How to do TDD with hardware
"Configure your browser for visual effects" error on chrome
What is the scancode of "Pause/Break" key?
Advertised disk space vs actual disk space
Why is not USB interrupt-driven?
How does hardware device (peripherals) implement the RO/WO registers?
Is there a way to trigger a hardware refresh (aka Device Manager) using .NET?
How to extract full monitor manufacturer/vendor ID in Windows? (as same as Linux hwinfo --monitor command)
How am I able to run Tensor Core instructions without actually having Tensor Cores?
Trying to programmatically disconnect microbit Pin
How are vendor IDs assigned for USB devices?
How to create a Docker named volume and populate it with default files?
How to create multiple vsphere VMs of different name, different CPUs and memory requirement using terraform using for_each
Boolean function optimizer package for Python
Representing 2 binary digits in hex for vhdl
DPDK Multi-process HW Timestamping issue
What's the difference between DMA Controller and I/O processor
Are data memory and instruction memory in data path L1 caches?
Difference between blocks and sectors
getUserMedia - Cannot access camera from two browsers at the same time
A KB is 2^10. Is a byte 2^0 or 2^1?
How to Detect Hardware Acceleration for OpenGL on Windows
Does endianess depend on processor or memory?
Get Serial Number of Boot Drive and other info
How to write data to a graphics card without using BIOS?
How can I change keyboard backlight timeout on XPG Xenia 16 RX gaming laptop?
Implementing hardware that divides an 8 bit number by 3 (11) in binary
How can I get current cpufreq in kernel code?
Listing available devices in python-opencv
CK (tCK, nCK) unit ambiguity in DDR3 standard/datasheets?